1. Technical Field
The present invention relates to a semiconductor circuit arrangement and particularly to an analog circuit having at least two field effect transistors which has a reduced mismatch caused by temperature and location.
2. Background Information
For future sub-45-nanometer complementary metal oxide semiconductor (CMOS) technologies, i.e. for field effect transistors with a gate length of less than 45 nanometers, new types of transistor architectures are currently being developed on the basis of what are known as multigate field effect transistors (MuGFETs). In the text below, multigate FETs are understood to be a broad term for field effect transistors having a multiplicity of gates or control electrodes, which also include transistors such as double-gate FETs, triple-gate FETs or FinFETs. The advantage of these new transistors over what are known as planar bulk MOSFETs, i.e. field effect transistors which are in planar form in the semiconductor substrate, is improved control of the short channel effects through a symmetrical arrangement of a plurality of transistor gates.
The present technologically favored arrangement includes two lateral gates, such as are known from FinFETs, or two lateral gates and an additional gate on the surface of a silicon fin, as are also known as triple-gate FETs. In this context, the silicon fin is also called a rib.
A drawback of such transistor architectures is their inadequate temperature response, however. On account of the three-dimensional topology of the field effect transistors and on account of the fact that the fins or ribs are normally surrounded on all sides by oxide, which is a poor conductor of heat, the power loss arising in the fins or ribs cannot be dissipated as efficiently as in conventional bulk transistors, for example.
Particularly for analog applications, the problem therefore arises that different temperatures in the fins or ribs, which are subsequently referred to as active regions, result in an increased mismatch caused by temperature differences. A need exists, therefore, for a semiconductor circuit arrangement for analog applications which has a reduced temperature-related mismatch.